MODEL QUESTION PAPER

 Subject: Nano Technology

MODEL QUESTION PAPER

Seventh Semester B.E. Degree Examination

ECE BRANCH

PART A

MCQ (“Multiple Choice Question.)

1.       Which one of the following is an advantage of nanotechnology?

a)       Increased stability

b)       Leakage of drug

c)       Low solubility

d)       All of the above

2.      What is Lithography?

a)      Process used to transfer a pattern to a layer on the chip

b)      Process used to develop an oxidation layer on the chip

c)      Process used to develop a metal layer on the chip

d)      Process used to produce the chip

3.      What is the standard form of SEM?

a)       Scanning Electron Microscope

b)       Scanning Electrode Microscope

c)       Scanning Electrical Microscope

d)       None of the above

4.      Which of the following application of tunnel diode has highest frequency of an solid based oscillator?

a)      MIIM diode

b)      Resonant tunneling diode

c)      RF diode

d)      All the above

5.      CNTs stands for ____________

a)      Carbon Nanotubes

b)      Carbon Nanotechnology

c)      Carbon Nanoscience and technology

d)      Carbon Nine Technology

6.      Which of the following application of tunnel diode has highest frequency of an solid based oscillator?

a)      MIIM diode

b)      Resonant tunneling diode

c)      RF diode

d)      All the above

7.      CNTs stands for ____________
a) Carbon Nanotubes
b) Carbon Nanotechnology
c) Carbon Nanoscience and technology
d) Carbon Nine Technology
Answer: a
Explanation: Carbon nanotubes, CNTs, are nanostructures with large application potential. Its structure consists of a single sheet of graphite rolled into a tube.

8.      The carbon contained in the negative electrode sublimates.
a) True
b) False
Answer: a

9.      What is Lithography?
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip
Answer: a
Explanation: Lithography is the process used to develop a pattern to a layer on the chip.

10.  Silicon oxide is patterned on a substrate using ____________
a) Physical lithography
b) Photolithography
c) Chemical lithography
d) Mechanical lithography
Answer: b
Explanation: Silicon oxide is patterned on a substrate using Photolithography.

11.  Positive photo resists are used more than negative photo resists because ___________
a) Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists
b) Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists
c) Negative photo resists are less sensitive to light
d) Positive photo resists are less sensitive to light
Answer: a
Explanation: Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists. Therefore, negative photo resists are-used less commonly in the manufacturing of high-density integrated circuits.

12.  The ______ is used to reduce the resistivity of poly silicon.
a) Photo resist
b) Etching
c) Doping impurities
d) None of the mentioned
Answer: c
Explanation: The resistivity of poly silicon is reduced by Doping impurities.

13.  The isolated active areas are created by technique known as ___________
a) Etched field-oxide isolation
b) Local Oxidation of Silicon
c) Etched field-oxide isolation or Local Oxidation of Silicon
d) None of the mentioned
Answer: c
Explanation: To create isolated active areas both the techniques can be used. Among them Local Oxidation of Silicon (LOCOS) is most efficient.

14.  The chemical used for shielding the active areas to achieve selective oxide growth is?
a) Silver Nitride
b) Silicon Nitride
c) Hydrofluoric acid
d) Polysilicon
Answer: b
Explanation: Selective oxide growth is achieved by shielding the active areas. Silicon nitride (Si3N4) is used for shielding the active areas during oxidation, which effectively inhibits oxide growth.

15.  The dopants are introduced in the active areas of silicon by using which process?
a) Diffusion process
b) Ion Implantation process
c) Chemical Vapour Deposition
d) Either Diffusion or Ion Implantation Process
Answer: d
Explanation: Two ways to add dopants are diffusion and ion implantation.

16.  To grow the polysilicon gate layer, which of the following chemical is used for chemical vapour deposition?
a) Silicon Nitride (Si3N4)
b) Silane gas (SiH4)
c) Silicon oxide
d) None of the mentioned
Answer: b
Explanation: Silicon Wafer is placed in a reactor with silane gas (SiH4), and they are heated again to grow the polysilicon layer by chemical vapor deposition.

17.  The process by which Aluminium is grown over the entire wafer, also filling the contact cuts is?
a) Sputtering
b) Chemical vapour deposition
c) Epitaxial growth
d) Ion Implantation
Answer: a
Explanation: Aluminum is sputtered over the entire wafer, it also fills the contact cuts.

18.  Chemical Mechanical Polishing is used to ___________
a) Remove silicon oxide
b) Remove silicon nitride and pad oxide
c) Remove polysilicon gate layer
d) Reduce the size of the layout
Answer: b
Explanation: The pad oxide and nitride are removed using a Chemical Mechanical Polishing (CMP) step.

19.  What is Piranha Solution?
a) It is a 3:1 to 5:1 mix of nitric acid and hydrogen peroxide that is used to develop the oxide layer on silicon substrate
b) It is a 3:1 to 5:1 mix of sulphuric acid and hydrofluoric acid that is used to clean silicon wafers removing organic and metal contaminants or photo resist after metal patterning
c) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to grow the oxide layer on the silicon
d) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to clean wafers of organic and metal contaminants or photo resist after metal patterning
Answer: d
Explanation: Piranha solution is a 3:1 to 5:1 mix of sulfuric acid and hydrogen peroxide that is used to clean silicon wafers of metal and organic contaminants or photo-resist after metal patterning.

 

PART B

Unit 1

·         Describe limitation of CMOS.

·         Define Nanotechnology.

·        List out the Applications of Nanotechnology in electronics

·        List out challenges faced by Nanotechnology.

·         Define nanotechnology.

·         Explain the MOSFET devices with suitable example?

·         List out the applications of nanotechnology in electronics.

·         What do you mean by CMOS.

·         What is a MOSFET?

·         What is scaling? why it is required? explain CMOS scaling.

Unit 2

·         Explain lithography with neat schematic diagram.

·         Explain in detail about the generation of photomask with suitable diagram.

·         Explain semiconductor etching.

·         How many types of lithography are there?

·         Give the applications Electron Beam Lithography.

·         Write a short note on Electron Lithography.

·         Explain the optical lithography with neat schematic diagram.

·         Explain the lithography method to fabricate nanomaterials.

·         With a neat sketch explain the working of Molecular Beam Epitaxy fabrication technique.

·         Explain in detail molecular beam epitaxy (MBE) in nanomaterial synthesis.

Unit 3

·         Compare the working of Scanning Electron Microscope and Transmission Electron Microscope.

·         Describe the working of atomic force microscope. What are the precautions required while operating AFM?

·         Make short note on:

o   Atomic Force Microscopy

o   Scanning Electron Microscopy

·         Explain with a neat diagram SEM setup and its use in analysing nanostructures.

·         Explain with a neat diagram TEM setup and its use in the characterization nanomaterials.

·         Explain the STM setup and discuss its advantages and disadvantages.

·         State the principle of SEM.

·         Give the advantages and disadvantages of SEM.

·         Give the advantages and disadvantages of AFM

·         State the differences between SEM and TEM.

·         Write the principle of TEM.

·         Explain with a neat diagram TEM setup and its use in analysing micro and nano fabrication.

·         Give the principle of STM.

·         Explain in detail size and surface, morphological analysis of nanostructures using SEM.

·         Explain with a neat diagram TEM setup and its use in analysing nanostructures.

·         How is SEM used for nanomaterial characterisation?

·         Explain use of TEM for NP-characterisation.

Unit 4

·         What is Resonant Tunneling Diode (RTD) used in?

·         What is a SED?

·         Write short note on Molecular Electronics.

·         How is zero [‘0'] logic represented in Single Flux Quantum (SFQ) logic?

Unit 5

·         What is a carbon nanotube?

·         Give the applications CNTs.

·         Explain the characteristics of CNT?

·         Write short note on (i) Carbon fullerenes (ii) Carbon Nanotubes

·         Make short note on:

o   Carbon Nanotechnology

·         Discuss the fabrication the carbon nanotubes and explain its structure.

·         Explain in detail Electrical, vibrational and mechanical properties of CNTs.

·         Discuss the applications of CNTs.

·         What is a carbon nano tube?

·         Give the types of CNTs.

·         Define Bucky ball.

·         Write any two properties of CNTs.

·         Explain the Quantum computing.

·         What is meant by single walled and multiwalled Carbon Nano Tubes.

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