Ferroelectric Field Effect Transistors

ntroduction

  • Ferroelectrics: dielectric crystals which show a spontaneous electric polarization and the direction of polarization can be reoriented by an external electric field
  • In ferroelectric memories, the direction of spontaneous polarization is used to store digital bits. 
  • Non-volatile electrically switchable data storage devices can be implemented. 
  • Typically implemented as a capacitor consisting of a thin ferroelectric film in between two conductive electrodes. 
  • The voltage pulse applied to the cap determines the polarity (“0” or “1”). 
  • For readout another voltage pulse is applied that determines whether or not polarization switched direction. 
  • Read process is non-destructive. 
  • Efforts focused on the development of ferroelectric FETs. 
  • Data read out in FeFET in non-destructive. 
  • FeFET has both memory and logic functions. 
  • FeFET is similar to MOSFETs, the gate oxide is a ferroelectric material

Principles of FeFETs

Ferroelectric memories are based on 1 (MOS) transistor–1 capacitor (1T1C) approach

Transistor is separated by a thick dielectric layer from ferroelectric cap

Reliability issues exist in fabrication of 1T1C cell

Figure (fig 1) shows the conventional DRAM, 1T1C ferroelectric cell and FeFET

Figure (fig 2) shows the layout of a FeFET

Figure (fig 3) shows the charge motion in a FeFET during one cycle of operation

Principles of FeFETs 

  • Vg>Vc: polarization vector P is directed toward Si 
  • Accumulation of electrons in channel, on state
  • Vg<-Vc: Pr is directed opposite, electrons are depleted
  • Non-destructive readout: sense the source-drain resistance

>FeFET memories: non-volatile, non-destructive readout, compact cell design

>Design structures for FeFETs and material aspects

As seen in the layout of FeFET, a stack of metal-ferroelectric-semiconductor is required for FeFET

Challenges in interfacing Si and ferroelectric:

  • Lattice mismatch must be as small as possible
  • Chemical reactions and intermixing should be minimized
  • Number of interface states should be less than 1012 eV-1cm-2
  • Formation of low-k dielectrics should be avoided
  • Ferroelectric must form a pinhole-free layer

Only a few Perovskite oxides are suitable for growth on silicon
Alternative gate stack layouts and various buffer layer configurations have been developed:
  • MFS: metal-ferroelectric-semiconductor
  • MFIS: metal-ferroelectric-insulator-semiconductor
  • MFMIS: metal-ferroelectric-metal-insulator- semiconductor
  • MF-ABO3: ferroelectric on a conductive oxide (no silicon)
Figure (fig 4) shows these alternatives
>Ferroelectric directly on silicon
  • The intermixing from Si to Perovskite leads to the degradation of the ferroelectric properties
>Buffer layer between ferroelectric and silicon
  • The effect of charge injection can be minimized by employing an engineered buffer sandwiched between the silicon and Perovskite layer
  • The buffer layer reduces the problem of intermixing silicon and ferroelectric
  • The gate oxide is comprised of two capacitors in series
  • The buffer layer weakens the electric field across ferroelectric
>Metal-ferroelectric-metal gate structures
  • MFMIS structure reduces the intermixing problems
  • However, it acts as a voltage divider
  • The gate voltage is divided according to the capacitance ratio of the MIS and MFM
  • The capacitance of the MIS diode should be large enough to allow the polarization reversal of MFM
  • The relatively large voltage is necessary to switch the ferroelectric capacitor (in the case of SiO2 insulator)
>Meta-Ferroelectric on a conductive oxide
  • The source-drain channel is replaced by a conductive oxide
  • These have similar growth conditions as ferroelectric
  • The aim is to modulate the conductivity of the conductive oxide by the polarization of ferroelectric
Electrical characterization of FeFETs















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